verilog 文本自动对齐:input output wire reg
1、之前有个脚本可以对齐input和output,但是没有解决wire和reg定义不对齐的问题。所以脚本改进了下,支持input output wire reg对齐
2、知识点总结:perl的字符串进行比较时需要使用eq,lt,gt,不能使用数字比较符==,>=,否则会出现逻辑错误。
#! /usr/bin/perl
use 5.010;
use strict;
my ($sec,$min,$hour,$day,$mon,$year,$weekday,$yeardate,$savinglightday) = (localtime(time));
$sec = ($sec < 10)? "0$sec":$sec;
$min = ($min < 10)? "0$min":$min;
$hour = ($hour < 10)? "0$hour":$hour;
$day = ($day < 10)? "0$day":$day;
$mon = ($mon < 9)? "0".($mon+1):($mon+1);
$year += 1900;
my $date = "${mon}${day}";
my $dir = '*.v';
my @all_files = glob($dir);
foreach my $file_name (@all_files){
open my $file_text,'<',"$file_name";
my $file_name_store = $file_name;
open my $new_file,'>',"new_file.v";
while(<$file_text>){
chomp;
if (/^\s*(input|wire|reg)\s*(\w.*)/){
if ($1 eq 'reg') {
printf $new_file "%s %-70s\n",$1,$2;}
else {printf $new_file "%s %-70s\n",$1,$2;}
}
elsif (/^\s*(input|wire|reg)\s*(\[.*\])\s*(\w.*)/){
if ($1 eq 'reg') {
printf $new_file "%s %-20s %-50s\n",$1,$2,$3;}
else {printf $new_file "%s %-20s %-50s\n",$1,$2,$3;}
}
elsif (/^\s*(output)\s*(\w.*)/){
printf $new_file "%s %-70s\n",$1,$2;
}
elsif (/^\s*(output)\s*(\[.*\])\s*(\w.*)/){
printf $new_file "%s %-20s %-50s\n",$1,$2,$3;
}
else {
print $new_file "$_\n";
}
}
close $file_text;
close $new_file;
system("cp new_file.v $file_name_store");
}
system("rm new_file.v");
效果如下: